testable blocks. ○ Constant-testability designs (C-testable designs). Soma 6 issues in testing and probe card design. CPU. RAM . IDDQ design guidelines. One DFT solution for systems on chip, based on IDDQ measuring concept is presented in this paper. The application of Reconfigurable neurai networks off chi . IDDQ Test With the IDDQ test method one determines the power consumption of a chip at a stable state (quiescent current). Then a chip is.
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With the IDD Q test method one determines the power consumption of a chip at a stable state quiescen t current. Such an increase of current might be owed to a physical defect of the chip.
Iddq testing & pattern generation in DFT(Design For testability)
Nevertheless, it is conceivable that despite the defect the functional behavior of the chip is correct. Thus the method of IDD Q testing is desihn a defect oriente d method than an er r o r oriented method. It may also be used to improve fo r eliabilit y of chips section Within the model of IDDQ faults all conceivable faults are considered which may increase power consumption. For example, the fault model includes bridgin g faultsgat e ox- id e shortstransisto r stuck on faultsand some stuc k at faults.
Design for Testability:IDDQ Test | pcb design
Functional Undetectable Defects With functiona l tests one tries to stimulate a fault and to propagate resulting erroneous signals to a primary output. In any stable state exactly one of the two transistors is conducting and therefore the output y is either connected to VD D or to VSS. Depending on the resistance of transistor channels, the value of the output signal y results from the voltage divider built by T 1 and T 2. It is also possible that despite the fault the voltage at the output y may be interpreted as the correct logic value.
Thus the logical behavior of the circuit may be correct. However, because of the effect of elect r o n migration desjgn fault may later cause dor ures after a longer period of operation.
Therefore on testabiliyy the IDD Q test it is possible to detect defects that can not yet be detected by functional tests.
An increased current can even be caused by a transistor stu c k open fault. Here the n-transistor is well suited tesgability transmit the value 0 and the p- transistor is well suited to transmit 1.
As a consequence it may happen that the transistor T 3 of the succeeding inverter is not perfectly locked, and therefore there is an erroneous current between VD D and VSS. Often such faults are also detected by functional tests as stu c k at faults. Further faults that cause an increase of quiescent current are bridgin g faultsand gat e oxide shorts.
This shall be demonstrated for the e xample of a hard combinatorial bridgin g fault section This will cause a high current because tfstability the short circuit.
For an automatic IDDQ test pattern generation dseign common test pattern generators it is very easy to model the bridgin g fault. Each pattern producing the signal 1 at the new output can be used as a test pattern. Since for computing IDDQ test patterns fault propagation can be omitted, there are more possible test patterns for a fault than for functional tests. Thus an IDDQ test needs fewer test patterns.
Thus for a given number of measurements one determines a set of test patterns obtaining a maximal fault coverage. Since the model of stu c k at faults does not deter- mine a unique kind of physical defect, some stu c k a t faults might increase quiescent current, whilest others do not.
Design for testability for SoC based on IDDQ scanning
Testtability this may not be true for an interruption of a wire. Thus the IDDQ method cannot replace functional tests but can extend such tests to improve defect coverage.
One should never use IDDQ measurements to reduce the number of functional test patterns. If all stu c k at faults could be detected by IDDQ measurements then the circuits obtained would be completely testable for stu c ffor at faults with only two test patterns.
Multipl e faults do not cause additional problems for IDDQ testing. For example it can be shown that when simple design rules are respected [ IDDQ test pattern generation also has to calculate the intensity of quiescent current. For this one may use an extended swit c h level simulation also considering realistic resistances of transistors. On the other hand, such simulations can also be used desugn determine the accuracy needed for an IDDQ measurement.
In order to receive meaningful results IDDQ tests should be restricted to such test patterns producing a low power consumption for correct chips. Applying the same test pattern to several correct chips one obtains different measured current values. The average value of that distribution denotes the typical quiescent current of a correct chip. But be- cause of deviations during manufacture actual values will differ from the expected value.
The threshold value for an IDDQ measurement should be determined according to the expected erroneous current. Then one has to compare the costs of both kinds of desjgn decisions: What are the expected costs if a testanility chip remains undetected and what does is cost to classify a correct chip as faulty? But since such a resistor within a supply line will reduce the applied voltage it has to be shorted by a transistor for normal operation of the chip.
As an alternative approach the resistor can be re- placed by a capacitor. Again, for normal operation it is shorted and unloaded. For testing, the transistor is opened and the capacitor is loaded by the quiescent current. If it extends a certain threshold value the chip fails the IDDQ test. This way it is possible to perform an IDDQ test without hardware overhead.
Built In Current Sensor [ With this technique self-tests are also possible. In order to apply an IDDQ test the circuit has to satisfy special properties. For example, as mentioned above, the correct circuit should have a very low quiescent current such that the erroneous current is easily detectable. Therefore the testtability may not use oscillators, and whenever there are dynamic storage blocks they have to be separated for the test. Testabliity pul l up resistors have to be disabled for the test mode, and for pa d drivers, analog cells, and bipolar sub- circuits a separate power supply is needed because they typically have a high power consumption.
Otherwise additional drivers have to be provided to force buses to default values whenever there is no actual write operation. Because of the necessary time for exact current measurement the circuit must be able to work at a slow clock rate.
Therefore if the chip itself is monitoring the system clock this must be deactivated for the test.
Furthermore, for r egula r structured circuits such as storage blocks, IDDQ tests are not of interest be- cause there are already specialized tests available with high defect coverage. Fu r the r Parameter Tests Since one reason for an increased quiescent current is that of illegal signal levels, the observation of voltage levels at critical signals is also an alternative to IDDQ tests.
Of course faults can also cause an increased current during the phase transient states.
To discover such effects one uses Flr T tests, observing t r ansient cur r en t. For example, in [ In particular, it is suitable for chips with low power supply.
For this task a method is described in [ Your email address will not be published. Posted on October 8, by ahmed farahat Idsq a comment. The Concept of Electronic Design Automation: Back-end Design Tools Physical Design: The Business of EDA: Leave a comment Cancel reply Your email address will not be published.